Path finding apparatus for switching network



Aug. 19,1969 A. MILEWSKI 3 5 PATH FINDING APPARATUS FOR SWITCHINGNETWORK Filed Dec. 29, 1966 6 Sheets-Sheet 1 BIHHEE] EIHIEE Aug. 19,1969 A. muzwsm 3,462,743

' PATH FINDING APPARATUS FOR SWITCHING NETWORK s sheets sheet 2 FiledDec. 29, 1966 STI 2 v 5 4 5T5 CI CL12 B CL23 CL CL45 CE 0 o J *\t i 0 v(Ame a Lmk IJA LmkAlB X As Subscnucr lJK Lmunmra Sub scribor X'J' K'Group AH Aug. 19, 1969 A. MILEWSKI 3,462,743

' PATH FINDING APPARATUS FOR SWITCHING NETWORK Filed Dec. 2'53, 1966 6Sheets-Shet 5 FIGA Aug. 19, 1969 A. MILEWSK! 3,462,743

PATH FINDING APPARATUS FOR SWITCHING NETWORK I Filed Dec. 29, 1966 6Sheets-Sheet 4 flv1959 v A. MILEV'VSKI 3,462,743

PATH FINDING APPARATUS FOR SWITCHING NETWORK FAIG. 7

Aug. 19, 1969 A. MILEWSKI 3,462,743

PATH FINDING APPARATUS FQR SWITCHING NETWORK Filed Dec. 29, 1966 sSheets-Sheet e Bi! posv- FIG.9

FIGS

United States Patent 3,462,743 PATH FINDING APPARATUS FOR SWITCHINGNETWORK Audrzej Milewski, St. Jeanuet, France, assignor to InternationalBusiness Machines Corporation, Armonk,

N.Y., a corporation of New York Filed Dec. 29, 1966, Ser. No. 605,756Claims priority, applicationRF Lrance, Jan. 4, 1966,

16 A Int. Cl. Gllb 13/00; G06f 7/00, /005 US. Cl. 340-172.5 ClaimsABSTRACT OF THE DISCLOSURE The invention relates to apparatus for freepath finding within a switching network of the plural matrix stage typecurrently found in telephony and specifically to finding a free pathbetween subscribers within a branch exchange.

Heretofore, such inquiry called for a reitrated scanning of the statusof those links, either by testing them directly in the network itself,or by testing an image network duplicating at all times all of thenetwork element status. The method used was generally involved, oftenlengthy and the circuits and devices used therewith were quitecomplicated, bringing about in some cases disturbances into the voicecircuit.

The present invention is directed to apparatus for receiving the logicaladdress designation of the matrices to which the subscribers aredirectly connected and for providing tentative address designations ofmatrices in all higher order stages necessary to establish a connection.The links between matrices for each subscriber are then testedconcurrently beginning with the connection between the matrix immediateto each subscriber and extending to the assumed matrix in the nexthigher order stage. If both links are free, the tentative addressdesignation for the matrices in that stage are assumed correct and theapparatus cycles to test the links to the next matrices. If eithertentative link is busy, other links to other matrices of the instantstage are examined to find free links and the tentative address assumedcorrect if found. If no sets of free links are found for that stage, theapparatus recycles and modifies the previously established link whichwas assumed correct to determine the addresses of a further pair of freelinks. The next succeeding stage is again tested and the operationcontinues.

Accordingly one of the objects of the invention is to provide anapparatus for free path finding within a switching network between agiven incoming line and an arbitrary output line.

A further object still of the invention is to provide an apparatus whichdoes not require protection circuits which in prior art systems keptbusy switches from being marked.

Another object of the invention is to provide control apparatusdecentralized to establish paths within large scale networks in a mannerindependent of the main control.

The invention has also for its object to make use of network structurefor obtaining from the address of lines to "ice be connected, theaddresses of those links found through the various possible pathsexisting between said two lines.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention, as illustratedin the accompanying drawings.

In the drawings:

FIG. 1 shows a switching network;

FIG. 2 illustrates details of a switching matrix;

FIG. 3 illustrates the interconnection law between ele ments of thenetwork of FIG. 1;

FIG. 4 is the main logic circuitry of the invention;

FIG. 5 shows details of logic address select circuits generally shownunder 28 on FIG. 4;

FIG. 6 discloses a timing circuit control device;

FIG. 7 shows a diagram of the input connections to register 29 of FIGS.4 and 5;

FIG. 8 shows a particular storage organization for a device embodyingthe invention;

FIG. 9 shows a detail of decoder 146 disclosed on FIG. 8.

SWITCHING NETWORK DESCRIPTION Referring to FIG. 1 there is shown aswitching network for a private branch exchange. The network basicallycomprises five switching matrix stages, 8T 8T ST;;, ST; and 8T four setsof links CL CL CL and CL extending between said successive stagematrices; lines CI referred to as subscriber lines or extensions sincethey correspond to telephone lines internal to the exchange; and linesreferred to as outgoing lines or trunk lines since they stand foroutgoing lines to public telephone network. Only the subscriber lines ofthe first matrix of the first stage have been disclosed. In FIG. 1,matrices have been drawn as blocks, and their internal configuration isconventional as may be seen on FIG. 2 wherein a three row (X X X and twocolumn lead (Y Y matrix is being shown. Said matrix switches Q Q Q Q Qand Q allow the coupling of any one of the row leads to any one of thecolumn leads. For example, closing switch Q electrically connects rowlead X to column lead Y Obviously both column lead number and row leadnumber may vary depending on the stage at which said matrix is found.

It may be seen from FIG. 1 that the first stage ST or input stagecomprises thirty-two matrices divided into four groups of eightmatrices, each matrix comprising sixteen row leads (that is sixteensubscriber lines or extensions per matrix, amounting to a total of 512extensions) and twelve column leads. Each of said matrices is identifiedby two coordinates:

Going from left, the first coordinate stands for the matrix group rank:0, 1, 2 or 3;

The second coordinate stands for the matrix rank into the group: 0, l,2. 7.

Each row lead into a matrix will also be assigned a coordinatecorresponding to its rank, said coordinate varying from 0 thru 15;similarly each column lead will be assigned a coordinate standing forits rank, said coordinate taking values such as 0, 1, 2 11.

From such numbering system, it may be readily seen that each lead,whether it is a column lead or a row lead, will be perfectly defined bya three coordinate address; the first two coordinate being thecoordinates of the matrix to which said lead belongs to, and the thirdcoordinate being said lead coordinate into said matrix.

The second stage ST comprises forty-eight matrices subdivided intotwelve groups of four matrices, each matrix comprising eight row leadsand four column leads.

Coordinates are assigned to those matrices and leads in accordance withthe same numbering principle as be- 3 fore; said coordinates may thentake the following values:

0,1, 2 11 for the matrix group rank;

0, 1 ,2 or 3 for matrix rank into a group;

0, 1, 2 7 for the row lead rank;

0, 1, 2 or 3 for the column lead rank.

The third stage 8T or network half-way stage, comprises forty-eightmatrices, just as the second stage, similarly divided into twelve groupsof four matrices, each matrix comprising four row leads and three columnleads. Still using the same numbering system, the various coordinateswill take the following values:

0, 1, 2 11 for the matrix group rank;

0, 1, 2 or 3 for matrix rank into a group;

0, 1, 2 or 3 for the row lead rank.

For reasons to be apparent subsequently, said stage column leads willnot be assigned coordinates. The network fourth stage ST comprisestwelve matrices the addresses of which are single coordinate addresses,said coordinate taking values 0, 1, 2 11. Each of said matricescomprises four row leads and four column leads which may take values 0,1, 2 or 3.

The fifth stage ST will only hold four matrices whose addresses aresingle coordinate ones, which may take values 0, 1,2 or 3. Each of saidmatrices comprises twelve row leads and twelve column leads which maytake values 0, 1, 2 11.

In order to readily define the laws according to which those links,extending between the various stage matrices, link said matrices, let Iand I stand for the respective coordinates of any matrix of the firststage, A and B those of an halfway stage matrix, and L the coordinate ofa matrix belonging to the fifth and last stage. The connection laws asschematically disclosed in FIG. 3 are as follows:

The column lead of coordinate A coming out of first stage matrix I] iscoupled to that row lead of coordinate I getting in matrix AI of thesecond stage;

That column lead of coordinate B coming out of matrix AI of stage two iscoupled to that row lead of coordinate I getting into matrix AB of stagethree;

One of the column lead getting out of matrix AB of stage three (for thepurpose of clarifying ideas that particular lead is going to be calledlead number one) is coupled to that row lead of coordinate B gettinginto matrix A of stage four. Since that lead going from stage AB on tothe next stage is unique, it becomes apparent that such lead does notneed any coordinate attached to it;

The row lead of coordinate L coming out of that matrix of stage four iscoupled to the row lead of coordinate A coming into matrix L of stagefive.

Furthermore, should K be the coordinate of that row lead coming intomatrix I] of stage one and M the coordinate of that column lead comingout of matrix L, it will be readily seen that such coordinate systemdefines:

The address of a subscriber line via the set of coordinates UK;

The address of a trunk line via the set of coordinates LM;

The address of a link from the first link from the first link set (CLvia the set of coordinates HA;

The address of a link from the second link set (CL via the set ofcoordinates AIB;

The address of a link from the third link set (CL via the set ofcoordinates AB; The address of a link from the fourth link set (CL viathe set of coordinates AL.

From the above, it should be readily seen, that there will be in suchnetwork only one path between a given subscriber line and a givenhalf-way matrix, as well as one path from a half-way matrix to a trunkor outgoing line. In effect, addresses IJK and AB of a subscriber lineand half-way matrix will obviously define all parameters of the one pathconnecting them. The same applies for addresses AB and LM. For finding afree path between some given subscriber line UK and some furtheroutgoing line LM, it is necessary to find a half-way matrix AB for theunique path defined by the set of coordinates IJK, AB, LM to be free.

A further characteristic of this network is that from second to fourthstage, coupling between stages are only via matrices belonging to thesame group (i.e., those matrices having like first coordinate A).However, connections between groups do happen, but they are solelyintended to realize connections between any two subscriber lines. Theseconnections are obtained via the halfway matrix column lead number twoand number three in accordance with the following law. Column leadnumber two of a given half-way matrix of address AB is coupled via ajunctor which address will also be AB, to column lead number three ofthe half-way matrix of address (A+1)B, it being understood that for A=11(maximum value of A in this herein example) A+1 becomes zero. Suchcouplings will be unidirectional in the direction of increasing valuesof A (arrow direction on FIGS. 1 and 3) owing to junctor unidirectionalcharacter. Hereinafter said junctors will only be described asunidirectional switches, the other ordinary functions (ringer control,ring back signals, tones, etc) not aiding in the understanding of theinvention.

Turning to FIG. 3, it is shown how it is possible to connect, viajunctor of address AB, two subscriber lines of respective addresses UKand IJK'. The path goes in succession through matrices I] of stage one,AI of stage two, AB of stage three, junctor AB, and matrices (A+1)B ofstage three, (A+1)I of stage two and finally IJ of stage one.

Still referring to FIG. 3, it may be readily seen, from the foregoingthat the necessary and sufficient condition, for establishing connectionbetween two subscribers of respective addresses UK and I'JK' is to finda junctor of address AB such that those paths from lead IJK to halfwaymatrix AB on one hand, and from lead I'J'K to matrix (A +1)B on theother hand are free.

Hereinafter, only connections between two extensions will be considered,since free path finding between subscriber line and outgoing line ortrunk may be obtained through a process and device similarly to thoseabout to be' described, but simpler and derived therefrom in a mannerwhich is obvious.

A device and method for finding a free path in a switching path betweena calling subscriber and a junctor and between a second subscriber andthis junctor is disclosed and claimed in an application, entitled FreePath Finding Device and Process Into a Switching Network, filed by M. B.Bastian and F. B. Bohy on July 11, 1966, Ser. No. 564,121

PATH FINDING PROCESS DEFINITION In order to find out within theswitching network just described, a free path between two subscribers ofrespective addresses IJK and IJK', the following steps are performed Alllink pairs belonging to the CL link set will be considered insuccession, each of said pairs corresponding to two links of respectiveaddresses HA and IJ'(A+ 1), with A increasing progressively from A=O,until a pair of two free links is found. If after going through allvalues of A up to the highest one (A=11 in the example) no free pair hasbeen found, there will not be a free path. If a free pair is foundbefore reaching the maximum value of A, then said pair will define somevalue for A, say A All link pairs belonging to the CL link set will thenbe considered. Each of these pairs correspond to two links of respectiveaddresses A IB and (A +1)IB with B increasing progressively from B=0,until a pair of two free links is found. If no free pair is found uponreaching the maximum value of B (B=3 in the example), step one isrepeated, taking for A the value A -l-l and for B the value zero. If apair is found, then said pair will define some value of B, say B A and Ewill then define a junctor.

Junctor A 13 is then considered. If it is idle, then a free path hasbeen found between leads UK and IJK. If it is not free, then the secondstep is repeated using B f-1. If at some particular time during search,the last junctor (AB=11.3 in the herein example) is considered and thisjunctor is not free, then no free path will ever be found.

PATH FINDING DEVICE DESCRIPTION (FIGS. 4 and 5 particularly) Most of thelogic circuits of FIGS. 4 and 5 are shown with single line connection soas not to obscure the invention, and it should be understood that thenumber of lines are determined by reference to the logic and to the datato be transferred.

The following logic symbols have been used throughou the figures:

Inverters are shown as squares with diagonals;

Logic gates acting as ANDs are shown as isoceles triangles;

Logic gates acting as ORs are shown as arcs of circles bounded throughtheir subtense.

The main elements shown in FIG. 4 are seven coordinate registersnumbered 21 thru 27, address selection logic circuits generally shownunder 28, a storage addressing register 29, a link storage memory 30, aread register (eventually write) 31, and finally data processing logiccircuits (shown in detail in FIG. 5

Registers 21 and 22 receive respectively coordinates I and J of thataddress IJK of a calling subscriber; registers 23 and 24 receivecoordinates IJ of that address IJK' of the called subscriber.

Register 25 is a binary counter which is set to zero at the beginning ofany search. It is incremented in the search as needed. Register 26 isconnected to register 25 so that its contents are always that ofregister 25 increased by one.

Register 27 is a binary counter, initially set to zero, whose contentsare incremented by one each time it receives a pulse.

All 0 fthese registers are multiposition registers suitable for storingthe coordinates of the respective subscribers. For example:

Registers 21 and 23 contain two bit positions (since the maximum decimalvalue of I is 3, that is 11 in binary form);

Registers 22 and 24 contain three bit positions (the maximum values of Ibeing 7, that is l 11 in binary form);

Registers 25 and 26 contain four bit positions (the maximum decimalvalue of A and A+1 is 11, that is 1011 in binary form);

Register 27 contains two bit positions (the maximum decimal value of Bis 3) Each of those seven registers are coupled to logic circuits 28,the latter circuits being intended to sequentially read out: addressesHA and 1J(A+l); then AIB and (A-i-1)IB; and finally AB corresponding tothe above mentioned three process phases. This selection process istimed as follows:

IJA at time T of phase P I'J'(A +1) at time T of phase P AIB at time Tof phase P (A+1)lB at time T of phase P AB during phase P A reversiblecounter 32 (see FIG. 4) upon the end of each phase and from the logicdata precessing circuits is counted up or down pulses in accordance withthe preceding phase result. Said counter comprises three outputs P P andP the outputs being respectively determined by the bit values 01, and 11of the counter contents. Whenever reset, said counter is reset to zero(in which case none of the above three circuits is fed) and goes tovalue 01 upon receiving a signal from a circuit S, controlling searchinitiation.

For the timed output T and T there is in FIG. 6 a circuit fororiginating the same. A latch 33 has two outputs respectively labeledcircuits T and T and is controlled via two input circuits E and E sothat Whenever a pulse is applied to E T is excited and T out off. Theopposite occurs whenever a pulse is applied to E Successive feed ing ofcircuits E and E is by AND circuits 34 and 35 each having three inputsapplied thereto.

The first input to each of those gates is from OR gate 36 whose twoinputs are P and P The second input to each of said gates is excitedwith clock pulses t.

The third input to gate 34 is from a feedback circuit from T while thethird input to gate 35 is from a feedback from circuit T The output fromgate 34 is applied to input E of latch 33 via an OR gate 37 whose secondinput S controls the initiation of a search as well as clock start.

After the device of FIG. 6 has been made operative by circuit S, gates34 and 35 will be enabled sequentially upon each clock pulse as long asthere is an input at P or P so that T and T will be in turn excited,each for a time corresponding to the time interval between twoconsecutive clock pulses.

Logic circuitry 28 is shown particularly in FIG. 5.

In order to emphasize the information held in register 29 during each ofsaid three phases P P and P the register has been conveniently shown asthree registers 29a, 29b, 290, which are linked to the logic circuitryin accordance with phase time during which said circuitry is active. Itshould be understood that such representation is only symbolic andintended to aid in the understanding only.

Storage 30, which may be of any (non-permanent) type, comprises at leastas many elements as there are possible addresses of the types IJA, AIBand AB, i.e. 384+l92+48=624. Actually said storage 30 will contain morethan 624 elements. The address for IJA in binary must include 111111011,that is 507 in the decimal system, because the coordinate A may onlytake twelve distinct values, while the four available binary order wouldallow sixteen combinations. The addresses of AIB and AB in decimalnumbers go from 0 to 191 for the first, and from O to 47 for the second.It is necessary to add to all addresses of type AIB a constant number atleast equal to 508 and to all addresses of type AB a number at least 192units higher than the previously chosen number. This determines thebinary number to be 10 digits in length.

The addresses may be readily obtained by circuits P and P as may be seenfrom FIG. 5

Circuit P enters a binary am into the tenth order of register 29 whichwill then hold a 1 throughout phase P All addresses transferred intosaid register during said phase (and which only use the first eightorders) will then be incremented by 512;

Circuit P simultaneously exicites orders 7, 8 and 10 of register 29.These orders will hold ls throughout phase P and all addressestransferred into said register during said phase (and which only use thefirst six orders) will then be incremented by 704 unit.

The sequential transfer of the various addresses is accomplished by thefollowing circuits, see particularly FIG. 5

Transfer of address IJA (phase P time T The output circuit 38 fromregister 21 (coordinate I) conditions succession, AND gate 39 whosesecond input is circuit T OR gate 40, and AND gate 41 whose second inputis circuit P The output circuit 43 from register 22 (coordinate 1)conditions in succession an AND gate 44 whose second input is circuit Tand OR gate 45, and an AND gate 46 whose second input is circuit P Theoutput 47 from the latter gate will then deliver information I at time Tof the first phase. The information is inserted into binary positions 5,6 and 7 of register 29a.

A first branch 48' of output circuit 48 of register 25 (coordinate A)conditions in succession an AND gate 49 whose second input is circuit Tan OR gate 50, and an AND gate 51 whose second input is circuit P Theoutput circuit 52 from the latter gate will then deliver information Aat time T of phase P Said information is introduced into binary position1, 2, 3, and 4 of register 29a.

Transfer of address IJ(A+l) (phase P time T The output circuit 53 fromregister 23 (coordinate I) conditions in succession an AND gate 54 whosesecond input is circuit T the OR gate 40 and the AND gate 41. The outputcircuit 42 from said latter gate will then deliver information I at timeT of phase P This information is inserted into binary positions 8 and 9of register 29a.

The output circuit 55 from register 24 (coordinate J) conditions insuccession an AND gate 56 whose second input is circuit T the OR gate 45and the AND gate 46. The output circuit 47 from this gate 46 will thendeliver the information I at time T of phase P Said information isinserted into the binary positions 5, 6 and 7 of register 29a.

The output circuit 57 of register 26 (coordinate A-i-l) conditions insuccession an AND gate 58, whose second input is circuit T the OR gate50, and the AND gate 51. The output circuit 52 from the latter gate willthen deliver the information A+l at the time T of phase P Thisinformation is introduced into binary positions 1, 2, 3 and 4 ofregister 29a.

Transfer of address AIB (phase P time T The branch 48' of output circuit48 of register 25 (coordinate A) conditions as seeen above the AND gate49 whose second input is circuit T other than OR gate 50, the outputcircuit of said gate 49 excites in succession, a second OR gate 59, anAND gate 60, whose second input is circuit P The output circuit 61 fromsaid latter gate will then deliver the information A at time T of phaseP This information is introduced into the binary positions 5, 6, 7 and 8of register 29b. The output circuit 38 of register 21 (coordinate 1)conditions in succession, as previously discussed AND gate 39, OR gate40. An output circuit from said gate 40 excites a second AND gate 62whose second input is circuit P The output circuit 63 from said latergate will then deliver the information I at time T of phase P Thisinformation is introduced into the binary positions 3 and 4 of register29b.

A first branch 64 of output circuit 64 of register 27 (coordinate B),conditions in succession, an AND gate 65 whose second input is circuit Tan OR gate 66, and an AND gate 67 whose second input is circuit P Theoutput circuit 68 from said latter gate will then deliver theinformation B at time T of phase P This information is introduced intopositions 1 and 2 of register 2911.

Transfer of address (A+1)I'B (phase P time T The output circuit 57 ofregister 26 (coordinate A-l-l) conditions the AND gate 58, whose secondinput is circuit T One output of gate 58 is transferred through OR gate59, causing the output circuit 61 of AND gate 60 to deliver theinformation A+1 at time T of phase P This information is introduced intothe binary positions 5, 6, 7 and 8 of register 29b.

Output circuit 53 of register 23 (coordinate I) together with AND gate54, OR gate 40 conditions AND gate 62. The output circuit 63 from thisgate will then deliver the information I at time T of phase P Thisinformation is introduced into the binary positions 3 and 4 of register29b.

A second branch 64" of the output circuit 64 of register 27 (coordinateB), is connected to an AND gate 69 whose second input is circuit T Theoutput of AND 69 is connected to OR gate 66. The output circuit 68 ofAND gate 67 will deliver the information B at time T of phase P Thisinformation is introduced into the binary positions 1 and 2 of register2%.

Transfer of address AB (phase P A second branch 48" of output circuit 48of register 25 (coordinate A) is connected to an AND gate 70 whosesecond input is circuit P The output circuit 71 from said latter gatewill then deliver information A during the third phase. This informationis introduced into the positions 1 and 2 of register 290.

A third branch 64" from output circuit 64 of register 27 (coordinate B)excites an AND gate 72, whose second input is circuit P The outputcircuit 73 from said latter gate will then deliver the information Bduring the third phase. This information is introduced into positions 1and 2 of register 290.

FIG. 7 discloses a logic diagram of all the select circuits exciting theregister 29. This diagram shows the actual number of connection lines ORgates are provided where there are a plurality of inputs for the sameregister bit position.

Referring to FIG. 4, the logic circuits for processing the informationread out of storage 30 will be described.

Whenever an address has been transferred into register 29 via logiccircuitry 28, the read register 31 then receives the elementary binaryinformation 1 or 0 according to whether the circuit elementcorresponding to that address is busy or free. The output circuit 74from register 31 is conditioned only if the information held therein isa I.

Circuit 74 includes a first branch 75 conditioning an AND gate 76, whosesecond input is circuit T The output circuit 77 of gate 76 is connectedto a one bit position register 78. The output circuit 79 of register 78conditions the first input of an AND gate 80.

A second branch 81 of circuit 74 conditions an AND gate 82, whose secondinput is circuit T The output circuit 83 of gate 82 is connected to aone bit position register 84 The output circuit 85 from said register 84conditions the second input of AND gate 80.

Operation of both preceding circuits is as follows. At time T of phase Pthe status of that lead of address IJA held in register 31 istransferred into register 78 via gate 76. At time T of the same phase Pthe status of that lead of address I'J(A+1) held in register 31 istransferred into register 84 via gate 82. At the end of phase P theoutput 86 of AND gate 80 will be excited if both leads HA and IJ'(A+l)are free. The same holds true for times T and T of phase P so that atthe end of the latter phase gate 80 will provide an output if both leadsAIB and (A+1)IB are free.

Circuit 86 includes a first branch 87 connected to and when there is anoutput from AND 80, incrementing reversible counter 32. This branchprovides for transferring to the next phase when the two leadsconsidered during the immediate phase have been found free.

A second branch 88 is taken from circuit 86 and includes a logicalinverter 89. The output circuit 90 of said inverter is then excited ifone, at least, of the two leads examined during the immediate phase hasnot been found free. In this case, it is then necessary to increment thecocordinate A or B, according to the phase.

For this, a first branch 91 conditions an AND gate 92, second input iscircuit P and third input is circuit T The output circuit 93 of saidgate 92 conditions, via an OR gate 94, and a circuit 95, and AND gate96. An output 97 of gate 96 causes the addition of one unit to thecontents of register 25 (provided that said contents are different fromthe maximum value of A, that is 11 in decimal form). The second input togate 96 is conditioned by a circuit 98 giving the condition 71%11. Thelatter circuit is obtained by a branch 99 from the output circuit 48 ofregister 25. This branch actually comprises four leads (since register25 is a four bit position register) which, when properly ANDed into anAND gate 100 (it sufiices to provide an inverter on the third bitposition lead, so as to form the bit combination 1011 corresponding to11 in decimal form), which provides on the output circuit 101 of saidgate 100 the condition A=11.

A logic inverter 102 changes this condition into A ll on circuit 98. Abranch 103- from circuit 101 will condition register 26 to reset sinceas was seen above, A+1 must be zero whenever A =11.

A second branch 104 from circuit 101, as well as a branch 105 fromcircuit 95, conditions an AND gate 106, whose output circuit 107 willindicate an overflow.

A second branch 108 is also taken from circuit 90. This branchconditions an AND gate 109, whose second input is circuit P and whosethird input is circuit T The output circuit 110 from said gate 109provides by an OR gate 111, and a circuit 112, a one unit addition tothe contents of register 27. In the case when said register contains itsmaximum value 3 in decimal form (that is 11 in binary form) a 1 additionwill reset said register to zero since it only holds two bit positions.In that latter case it is also necessary to further detect thesimultaneous occurrence of those two conditions: Add 1 to B" and B=3,since this implies a return to phase P and a one unit addition to A. Forthis, a branch 116 is taken from the output circuit 64 of register 27,said branch having its two leads (since register 27 comprises two bitpositions) condiitoning an AND gate 117. The output circuit 118 fromsaid gate 117 is then conditioned by the binary combination 11 that is 3in decimal form; said circuit 118, as well as a branch 121 circuit 112,conditions an AND gate 122. The output circuit 123 of said gate 122 willthen be excited if the two previous conditions are presentedsimultaneously. A one unit addition to register 25 is then obtained bybranch 124, circuit 123 conditions OR gate 94. Insofar as going back tophase P this action is controlled via branch 125 from circuit 123, by ORgate 126, and by circiut 127, feeding the input decrement of reversiblecounter 32.

The output circuit 74 from register 31 comprises a third branch 128conditioning an AND gate 129, whose second input is circuit P The outputcircuit 130 of said gate 129 will then be excited during phase P ifregister 31 holds a 1 during this same phase, that is if the junctor ABbeing examined is free. In that case, the search is ended, and a firstbranch 131 from circuit 130 carries a signal indicative of search end.This initiates the establishment of the found path, together with memoryupdating, and resetting to zero of registers 25 and 27. When there is nooutput on circuit 130 from gate 129, the junctor being examined (AB) isbusy and it is necessary to go back to phase P and to add one unit to B.This is done by the following circuits: A second branch 132 from circuit130 including an inverter 133, permits an output on circuit 134indicative of the condition AB not free. A first branch 135 from circuit134 conditions an AND gate 136, Whose second input is circuit P and theoutput circuit 137 from said gate 136 conditions the OR gate 126. Asecond branch 138 from circuit 134 conditions OR gate 111.

DETAILED DESCRIPTION OF A COMPLETE PATH FINDING PROCESS BETWEEN TWOSUBSCRIB- ERS OF RESPECTIVE ADDRESSES IIK AND I'JIK As soon as thetelephone line scanning system (which is not being described since itdoes not form a part of the present invention) has detected the callingsubscriber address IJK, and the called subscriber address IJ'K', thecoordinates I, I, I' and J of said addresses are entered respectivelyinto registers 21, 22, 23 and 24, and search initiation circuit S isenabled. At that time, registers 25 and 27 both hold therein the valueand register 26 value 1.

Circuit P is then excited, and also circuit T upon the first clockpulse. The address 110 is transferred into register 29 and registers 31then 78 hold then a 1 or a 0 according to whether lead 110 is free orbusy.

Upon the next clock pulse, circuit P is still excited because counter 32has not been incremented and circuit T is cut OE and T excited. AddressIJl is transferred into register 29, and registers 31 and subsequently84 receive the binary status of lead IJl.

If one at least of leads H0 or Ill is not free, gate will stay disabledall throughout phase P and at time T of said phase, gate 92 will beenabled and an increment signal will be transferred into circuit 97,register 25 will then indicate 1 and register 26 2 (binary number 10).

Since counter 32 has not received any increment, circuit P will continueto provide an output and phase P will be repeated during which phase thestatus of leads Ill and IJ-2 is going to be examined. Some number ofsuccessive phase P will then be repeated until some value of A isreached, say A such that leads 11A,, and IJ'(A +1) are both found free.

If after having tried all successive values of A, the last two leads ofthe set that is I111 and 1'] '0 are not both free, detection by gate 106of those simultaneous conditions Add 1 to A and A=l1 will cause anoverflow and search end signal to be sent into circuit 107.

If on the contrary a suitable value A is found, gate 80 is enabled and asignal is sent by circuits 86 and 87 to counter 32. Circuit P is thenexcited to initiate phase P On the first clock pulse after P excitation,circuit T is excited, so that address A IO is transferred into register29. Register 31, then 78, will contain a l or a 0 according to whetherlead A IG is idle or busy.

On the following clock pulse, P being still excited, T is cutoff and Texcited. Address (A+l)I'O is transferred into register 29. Register 84will thereafter contain the binary status of lead (A -|1)I'0.

If one at least of the two leads A IO and (A,,+1)IO is not free, gate 80will stay disabled all throughout phase P At time T of said phase gate109 will be enabled, and an increment signal will then be sent viacircuit 112 to register 27. Register 27 will then be set to 1.

Since counter 32 has received an increment order, circuit P will go onbeing excited and a new phase P will be repeated, during which phase,the status of leads A n and (A l )I '1 will be examined.

After some number of successive phase P a value of B, say B,,, may befound such that both leads A,,IB and (A,,+ 1 )I'B are found free.

If after having tried all successive values of B, the last two leads ofthe set, that is A 13 and (A +1)I'3 are not both free, the detection bygate 122 of those simultaneous conditions Add 1 to B and B=3 will sendto counter 32 (via circuits 123, 125, and 127) a signal ordering it todecrement by one, that is to go back to phase P and on the other hand tocommand (via circuits 123, 124, and 97) a one unit addition to register25. It should be noted that register 27 is reset automatically bycircuit 112 adding one unit to B. A new P phase will then be initiatedby examining those leads of the first set, starting from the new valueof A that is A,,+1.

If on the contrary, a suitable value H has been found, gate 80 isenabled at time T of phase P and an increment signal is then sent viacircuits 86 and 87 to counter 32: circuit P is then excited, such that afirst phase P is initiated.

As soon as P is excited, the address A B held in registers 25 and 27 istransferred into register 29. Binary status of junctor A B will thenshow up in register 31:

If said status corresponds to a zero, that is junctor A B not free, gate129 stays disabled and the output circuit 134 from inverter 133 isexcited. A signal is then sent into circuit 127 via gates 136 and 126causing counter 32 to count down, and on the other hand into circuit 112causing a one unit addition into register 27, via gate 111. A new Pphase is then initiated starting from values A I(B +l) and (A +1)I'(B+l) and so on; If said status corresponds to a 1, that is junctor A Bidle, gate 129 is enabled and an end of search signal is then sent intocircuit 131. Junctor A B then defines a free 1 1 path between leads UKand I'JK' such free path going through the following elements insuccession:

Subscriber line IJK,

Matrix I] of stage one,

Link IJA (set CL Matrix A I of stage two,

Link A IB (set CL Matrix A B of stage three, Junctor A B Matrix (A,,+l)Bof stage three, Link (A,,-}-l)lB (set CL Matrix (A,,+1)l of stage two,Link I'J(A +l) (set CL Matrix I'J of stage one, Subscriber line IJK'.

The switches to be closed in the enumerated matrices to establish thepath so determined is via the connectlon law disclosed on FIG. 3, whichis:

sponding to the row lead of coordinate I and to the column lead coupledto junctor A B For matrix (A +1)l' of stage two, that switch ofcoordinate J B,,;

For matrix PI of stage one, that switch of coordinate At the end of asuccessful search, all of the coordinates I, J, I, I, A and B as well asA +1 are contained in registers 21, 22, 23, 24, 25, 26 and 27. Themarking circuit addressing as well as memory updating may be readilyeffected from the output circuits from said register. After suchoperations have been accomplished, the subject registers are reset tozero (except for register 26 which then obviously hold a 1).

DESCRIPTION OF A PARTICULAR MEMORY ORGANIZATION FIG. 8

The storage of FIG. 8 is designed to meet the invention generalrequirements. Its main advantage is in providing automatic storageupdating and simplifying the addressing of said storage.

In accordance with said implementation, a bistable magnetic core is madeto thread each link and each junctor lead (a junctor lead beingunderstood as that lead coupling two half-way stage matrices via ajunctor). Each core will therefore be subject to field variations as aresult of current through the corresponding lead. With parametersproperly chosen (core characteristic, current flowing through the leads)the magnetic status of a core will reflect, at any time, the busy ornonbusy status of that lead with which said core is associated, and toread this status via two coincidence addressing circuits and a read outcircuit. The addressing of the storage is from register 29 whichsequentially receives the addresses of links to be examined.

In FIG. 8, there is shown schematically circuits for successivelyaddressing from register 29:

(1) A link of given address ija from the first link set 12 (2) A link ofgiven address aib from the second link set CL and (3) A junctor lead JRof given address ab;

Cores W W and W are respectively associated with these three leads.

As in the previous case, register 29 has been symbolically shown inthree sections, 29a, 29b, and 290, corresponding to the three phases P Pand P The nine output circuits from register 29 are divided into threebranches 139, and 141 comprising respectively:

Nine output circuits for the first branch 139,

Eight output circuits for the second branch,

Six output circuits, corresponding to the first six bit positions forthe third branch.

The nine leads of branch 139 condition nine AND gates whose second inputis circuit P The connection leads to the drawing being generally shownunder a single line connection. The nine gates have been shown under asingle gate, labelled 142. The nine output circuits from gate 142,generally shown under 143, then divide into two groups 144 and 145comprising respectively: five leads (corresponding to the first fiveregister bit positions) and four leads (corresponding to the 6th, 7th,8th and 9th bit positions of the register). The first group 144 excitesa first decoder 146, and the second group a second decoder 147.

The decoder 146 includes twenty-four output leads each of themcorresponding to one of the twenty-four binary numbers which may beformed by the first five bit positions of register 29. (It should berecalled that coordinate A may only take twelve distinct values out ofthe sixteen values permitted by the four bit positions said coordinateoccupies.) Decoder 147 includes sixteen output leads, each of themcorresponding to one of those sixteen binary numbers which may be formedby the last four bit positions of register 29. Each of said decoders mayinclude a set of AND gates whose input comprises logic inverters dividedin accordance with each combination desired. In FIG. 9 has been shownone of the gates of decoder 146 (one giving the combination 10110).

The output leads from decoders 146 and 147 corresponding to addressz'ja, that is 148 and 149, respectively condition two AND gates and 151whose second input is circuit t which as was seen above delivers clockpulses. The gates are necessary because of the fact that the coreaddressing pulses must be shorter than those tarnsmitted by circuits 148and 149 which actually correspond to those delivered by circuits T and TThe respective output circuits 152 and 153 of gates 150 and 151 make upthe addressing leads of core W Assuming that address ija is for example100110110, output leads 148 and 149 respectively correspond to those ANDgates of decoders 146 and 147 giving the combinations 10110 and 1001.Each of the remaining cores threaded through the links of the CL set,may be associated with two addressing leads coming out of respectivedecoders 146 and 147. Since the outputs of said decoders allowcombinations, there are 384 leads.

The wiring is similar to that of a core matrix comprising twenty-fourrows and sixteen columns. For example, lead 152 representing thecombination 10110 will be common to all cores of the CL link set, thefirst five address ranks of which hold that combination (that istwenty-four cores). Similarly lead 153 representing combination 1001will be common to all cores of the CL link set, the last four addressranks of which hold that combination (that is sixteen cores).

Besides being threaded by that link of address ija together with the twoaddressing leads, core W is further threaded by a read out lead R whichis, as in all conventional storage, common to all of the storage cores,since one core is read at a time. The lead R is coupled to register 31whose role is the same as in the previous example.

Branch 140 from register 29 (eight total) are divided, after goingthrough the AND gates generally shown under 154 and controlled bycircuit P into two groups 155 and 156 of four leads each. Said twogroups are respectively coupled to two decoders 157 and 158 comprisingsixteen output leads for the first, and twelve for the second. Combinedby twos, said output leads make up 192 pairs of leads to address thosecores of the CL link set. Said address leads through AND gates such as159 and 160 controlled by circuit 2. for the same reasons as previouslymentioned. In the fig. only core W addressing circuits have been shown.

Still in accordance with the same principle, those leads from branch 141(six in total) are divided after going through those AND gates generallyshown under 159 and controlled by circuit P into two groups 160 and 161of three leads each, corresponding to register 29 bit positions 1, 2,and 3 for the first group and 4, 5 and 6 for the second one. These twogroups are coupled respectively to decoders 162 and 163 comprising eightoutput leads for the first and six for the second. Combined by twos,said leads make up 48 pairs of leads to address those cores of thejunctor lead set. Said addressing leads go through gates such as 164 and165 controlled by circuit t. In the fig. only the addressing circuits ofcore W have been disclosed.

The unit operation is as follows:

When an address IJA is set in register 29 at time T of phase P core W isaddressed via decoders 146 and 147 and read wire R sends into register31 the status of link IJA;

At time T of phase P register 29 contains address IJ' (A+1), and it willbe core W that will be addressed via decoders 146 and 147. Lead R sendsthe status of link 1'! (A+1) into register 31 for processing;

At time T of phase P register 29 holds address ALB and core W isaddressed via decoders 157 and 158. The status of link AIB istransmitted to register 31 by lead R for processing;

At time T of phase P register 29 holds the address (A-i-DIB and it iscore W that will be addressed via decoders 157 and 158. The status oflink (A+l)IB is transmited into register 31 via conductor R for process-At phase P register 29 holds address AB and core W is addressed viadecoders 162 and 163. The status of junctor lead AB is transmitted toregister 31 via lead R for processing.

While the invention has been particularly shown and described withreference to a preferred embodiment thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade therein without departing from the spirit and scope of theinvention.

What is claimed is: 1. Apparatus for determining a free connective pathbetween a plurality of matrices in a network of a plurality of stages ofmatrices in which each matrix includes elements for selectivelyestablishing a connective path to other matrices including:

an address register containing a plurality of orders for storage of dataindicative of a path between a plurality of matrices;

means for initially setting into the lower orders of said addressstorage register, the matrix designation of said plurality of matricesbetween which a path is required and in all other orders the designationof matrices to complete a tentative path;

sensing means responsive to the address data contained in said storageregister for selectively detecting the free or busy connection betweenconnected matrices defined by said data and providing an indicationthereof;

phase generating means to control the readout of successive orders ofsaid address register to said sensing means in response to the freecondition of the connective link referrable to the order then beingconsidered to verify the tentative path or to initiate a modification inthe path so indicated;

means responsive to an output from said sensing means that a linkbetween matrices is busy to modify the matrix designation contained inthe order of said address register then being considered and controllingsaid phase generating means to iterate the step of immediately above;

and means responsive to an indication from said address register thatall matrices referrable to that order have been considered to controlsaid phase generative means to regress to a lower order to establish adifferent path than the one originally assumed correct.

2. The apparatus of claim =1 wherein said generating means includes abidirectional counting device responsive to the output of said sensingdevice indicative of a free path between matrices being considered forincrementing to a successive phase; said counting device beingresponsive to the output of said sensing device indicative of a busypath and an output from said address register that all matrixconnections referrable to the order being considered have beenconsidered for decrementing said counting device to initiate theprevious phase.

3. The apparatus of claim 2 wherein said sensing means includes amagnetic core associated with each link between matrices selectable bysaid address contained in said address register and a sense windingcontained in each said core and responsive to the selection process forproviding an indication of the state of said core and consequently thecondition of said link.

4. Apparatus for determining a free connective path between two matricesreferrable to subscribers connected immediately thereto in a switchingnetwork including a plurality of stages of matrices in which each matrixincludes elements for selectively establishing a connective path toanother matric including:

an address register containing a plurality of orders for storage of dataindicative of the path between the subscriber matrices;

means for initially setting into the lowest orders of said addressregister the matrix designation of the subscriber matrices and in allother Orders designations of matrices and connective elements by matrixdesignation to complete a tentative path between the subscribermatrices;

sensing means responsive to the address data contained in said storageregister for selectively detecting the free or busy connection betweenthe connected matrices and links defined by said data and providing anindication thereof;

phase generating means to generate time signals to establish successivecircuit conditions within said apparatus wherein the links betweensuccessive matrices may be tested;

means forming part of said sensing means and responsive to theincrementing time signals to enable the selective transfer of data bysuccessively higher order from said address register to said sensingmeans;

first control means responsive to the output of said sensing meansindicative that both links then being considered are free for advancingthe phase generating means to the next phase;

second control means responsive to the output of said sensing meansindicative that either link is busy for modifying the matrix designationof the order of said address register then being considered to ascertainwhether the linking so defined are free and third control meansresponsive to an indication from said address register that all matricesreferrable to that order have been considered to decrement said 15 phasegenerator to establish a difierent path from that found free in a lowerorder and assumed correct as a portion of the entire path.

5. The apparatus of claim 4 wherein said sensing means includes amagnetic core associated with each link between matrices selectable bysaid address register, and a sense winding contained in each said coreand responsive to the selection process for providing an indication ofthe state of said core and consequently the condition of said link.

I 6 References Cited UNITED STATES PATENTS 3,300,764 1/1967 Doelz et a1340-1725 3,287,703 11/1966 Slotnick 340172.5 3,287,702 11/1966 Borck eta1 340172.5 3,273,126 9/1966 Owen et a1 340172.5 3,241,124 3/1966Newhouse 340172.5

0 GARETH D. SHAW, Primary Examiner

